The present invention relates generally to electronic integrated circuits, and more particularly, to an asymmetrical semiconductor device used to protect integrated circuits against potential damage which can be caused by electrostatic discharge (ESD) events for bulk CMOS and silicon-on insulator (SOI) technology.
Integrated circuits are extremely sensitive to ESD pulses and are susceptible to physical damage and destruction from the high voltages and currents which can be generated by ESD events. ESD is a high voltage electric pulse of short duration which is usually caused by static electricity. ESD pulses normally originate from the handling of the integrated circuit during manufacture, assembly and installation. When an ESD pulse occurs on a transistor, the extremely high voltage of the ESD pulse can break down the transistor and can potentially cause permanent damage. Consequently, the input/output pads of an integrated circuit need to be protected from ESD pulses so they are not damaged.
Integrated circuits and the geometry of the transistors which comprise the integrated circuits continue to be reduced in size and the transistors are arranged closer together. A transistor""s physical size limits the voltage the transistor can withstand without being damaged. Thus, breakdown voltages of transistors are lowered and currents capable of overheating components are more frequently reached by the voltages and currents induced by an ESD event. Additionally, recent advances in technology have produced devices which can fail at voltage levels lower than the triggering voltages of known ESD protection circuits. Thus, there is a need for improved ESD protection circuits with lower triggering voltages.
In order to have a robust ESD protection device, the device must be able to handle large currents during a short period of time, as an ESD pulse may be approximately 200 ns in duration. Currently, the trend in ESD protection devices is to use NFET based ESD devices operating under avalanche conditions. Graphs of current versus voltage for a typical NFET and for an asymmetrically NFET according to the invention are shown in FIG. 1. During an ESD event, the voltage rapidly increases until it reaches the triggering voltage. When the triggering voltage is reached, the NPN bipolar transistor beneath the MOSFET transistor turns on and the voltage is clamped at the sustaining voltage. Typical NFET devices have a low beta and low substrate resistance. These two characteristics result in the NFET devices having a high snap-back or trigger voltage and a high sustaining voltage, respectively. The high trigger voltage and high sustaining voltage provide a device with a high degree of reliability, but are not good characteristics for an ESD protection device. For ESD protection, the ESD device should trigger as early as possible, that is the trigger voltage should be as low as possible. The sustaining voltage should also be as low as possible. As the trigger voltage and the sustaining voltage decrease, the ESD device turns on at lower trigger voltages and It2, that is the second breakdown current in the MOSFET, is increased, thus creating a more efficient ESD protection device.
A method and an apparatus thereof for increasing the second breakdown in a MOSFET to create an ESD robust device is provided for both bulk CMOS, BiCMOS, RF CMOS and SOI technologies. An asymmetrical FET with a lower triggering voltage and lower sustaining voltage compared to known devices is achieved. In one embodiment of the invention, first and second diffusion regions of a standard type are formed in a substrate. A gate is formed over the substrate between the first and second diffusion regions. A non-self-aligned buried resistor (BR) well implant is provided under the first diffusion region. The resistor well implant extends deeper into the substrate than either the first or second diffusion regions, thereby forming an asymmetrical device. Additionally, an extension implant region may be arranged in either one or both of the diffusion regions. The resistor well implant is used as a compensating implant to make the NPN parasitic bipolar transistor more efficient, thereby increasing the device""s beta.
In another embodiment of the invention, a source region and a drain region are formed in the substrate. A gate is formed over the substrate between the source and drain regions. A compensating implant region, implanted after the source/drain regions are formed, is arranged under the source region. The compensating implant region extends deeper into the substrate than either of the standard source and drain regions. Further to this embodiment, an extension implant region is preferably formed in at least one of the source and drain regions. The extension implant region extends from the source or drain region under the gate.
The ESD protection device of the first described embodiment can be created without an additional masking sequence, since the BR resistor well is implanted or otherwise formed prior to the first and second diffusion regions in the same areas. However, in the second described embodiment of the invention, an additional masking step may be necessary. In this case, the compensating implant is preferably implanted on the source side of the device at a predetermined angle after the source/drain implant on the device occurs. In a preferred embodiment, the asymmetrical ESD protection device is formed from a zero-Vt device. A zero-Vt device is also known as a natural device. Additionally, the extent to which the gate, the extension implant region and the compensating implant region overlap each other can be varied because the BR compensating implant mask is non-self-aligned to the gate structure in this embodiment.
The present invention provides an improved ESD protection device which can be easily made and requires the addition of only one mask or no additional masks. Moreover, the ESD protection device of the present invention has a high beta which leads to a lower sustaining voltage and a higher second breakdown current. Additionally, the trigger voltage of the device is lowered to provide protection at low trigger voltages.